ITC 2015 - CALL FOR TUTORIALS PARTICIPATION

Scope

The Test Technology Educational Program (TTEP’15) of the TTTC is offering 12 half-day tutorials during the weekend before the ITC test week. This year, the TTEP tutorials will touch the most important topics of the test scenario, problems and solutions taught by recognized experts of the field.

You can get detailed information on the TTEP website: http://ttep.tttc-events.org/ttep/tutorials.html

Registration

Register for Test Week Tutorials at the ITC Registration Page http://itctestweek.org/register.

Conference, tutorial and workshop registration can all be done with our easy to use on-line registration form.

Registration is NOW open!!

Program

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October 4, 2015 (Sunday)
Morning

Tutorial 1:
MIXED-SIGNAL DFT & BIST: TRENDS, PRINCIPLES, AND SOLUTIONS

by Steve SUNTER

We analyze recent trends in IC processes and design, and implications for test, then look at trends in testing. Next, we discuss trends in ad hoc DFT and fault simulation, then all relevant IEEE DFT standards: 1149.1, .4, .6, .7, .8, P1149.10, and 1687. The trend analysis concludes with a review of BIST techniques. Addressed circuits include PLL/DLL, ADC/DAC, SerDes/DDR, general I/Os, and last but not least, random analog. Next, seven essential principles of practical analog BIST are presented. Lastly, we discuss practical DFT techniques, ranging from analog defect simulation and the classic analog bus, to oversampling and undersampling methods that greatly improve range, resolution, and reusability.

Tutorial 2:
TEST OPPORTUNITIES AND CHALLENGES FOR SECURE HARDWARE AND VERIFYING TRUST IN INTEGRATED CIRCUITS

by Domenic FORTE, Mohammad TEHRANIPOOR

The migration from a vertical to horizontal business model has made it easier to introduce many vulnerabilities to electronic component design and supply chain. In the first part of this tutorial, we discuss the major issues that must be addressed including securing hardware, verifying trustworthiness of integrated circuits, unique key generation, side-channel attacks and more. . In the latter two parts of this tutorial, we will place more emphasis on detection and prevention of hardware Trojans and counterfeit electronic parts and discuss how test can help. In this tutorial, we will cover (i) An introduction to hardware security and trust (physically unclonable functions, true random number generation, hardware Trojans, counterfeit ICs, side-channel attacks, supply chain vulnerabilities, etc.), (ii) Background and motivation for hardware Trojan and counterfeit prevention/detection; (iii) Taxonomies related to both topics; (iv) Existing solutions; (v) Open test challenges; (vi) Design for security and trust, (vii) New and unified solutions to address these challenges.

Tutorial 3:
BEYOND DFT: THE CONVERGENCE OF DFM, VARIABILITY, YIELD, TEST, DIAGNOSIS AND RELIABILITY

by Srikanth VENKATARAMAN, Robert AITKEN

The tutorial goal is to show how design for yield (DFY) and design for manufacturability (DFM) are tightly coupled into what we conventionally think of as test. As process geometries shrink, the line between defects and process variation blurs to the point where it is essentially non-existent. As feature sizes reduced, systematic mechanism-limited yield loss began to appear as a substantial component in yield loss due to the interaction between design and manufacturing. The basics of yield and what fabs do to improve defectivity and manage yield are described. DFM techniques to analyze the design content, flag areas of design that could limit yield, and make changes to improve yield are discussed. In DFM/DFY circles, it is common to speak of defect limited yield, but it is less common to think of test-limited yield, yet this concept is common in DFT (e.g. IDDQ testing, delay testing). Test techniques to close the loop by crafting test patterns to expose the defect prone feature and circuit marginality through ATPG, and by analyzing silicon failures through diagnosis to determine the features that are actually causing yield loss and their relative impact are covered.

Afternoon

Tutorial 4:
PRACTICES IN HIGH SPEED I/O TESTING

by Salem ABDENNADHER, Saghir SHAIKH

This tutorial presents the existing industrial techniques to meet the ever increasing test complexity of High Speed IO's (HSIO). It first describes the basic design of both serial and parallel HSIOs and then presents various testing methods of HSIO, such as timing margining, voltage margining, compensation testing, leakage testing and etc. The examples of all these test methods will be presented with special emphasis on DFT and BIST based approaches of HSIO testing and their suitability to the production level environment.

Tutorial 5:
TESTING OF TSV-BASED 2.5D- AND 3D-STACKED ICS

by Erik Jan MARINISSEN

Stacked ICs with vertical interconnect containing fine-pitch micro-bumps and through-silicon vias (TSVs) are a hot-topic in design and manufacturing communities. These 2.5D- and 3D-SICs hold the promise of heterogeneous integration, inter-die connections with increased performance at lower power dissipation, and increased yield and hence decreased product cost. However, testing for manufacturing defects remains an obstacle and potential showstopper before 3D-SICs can become a reality. There are concerns about the cost or, even worse, feasibility of testing such TSV-based 3D chips. In this tutorial, we present key concepts in 3D technology, terminology, and benefits. We discuss design and test challenges and emerging solutions for 2.5D- and 3D-SICs. Topics to be covered include an overview of 3D integration and trend-setting products such as a 2.5D-FPGA and 3D-stacked memory chips, test flows and test content for 3D chips, advances in wafer probing, 3D design-for-test architectures and ongoing IEEE P1838 standardization efforts for test access, and 3D test cost modeling and test-flow selection.

Tutorial 6:
DELAY TEST: CONCEPTS, THEORY AND RECENT TRENDS

by Suriyaprakash NATARAJAN, Arani SINHA

This tutorial covers fundamental concepts, recent ideas and industry practices on validating and testing integrated circuits for speed failures. Main areas covered are: (a) defects and marginalities such as crosstalk, voltage droop, multiple-input switching and charge-sharing that result in speed failures, (b) delay fault models and fault sensitization conditions, (c) classical and advanced metrics to measure delay test quality and methods to improve them, (d) design-for-test to facilitate application of delay tests, (e) algorithms for test generation, fault simulation and diagnosis, including cell-aware and those targeting memory shadow and time borrowing logic, and (g) applications in post-silicon validation, speed binning and in-field reliability using industry case studies.

October 5, 2015 (Monday)
Morning

Tutorial 7:
HIERARCHICAL TEST FOR TODAY’s SoC and IoT

by Yervant ZORIAN

Today’s SoC and IoT design teams, use heterogeneous IP blocks from numerous sources, and multi-level hierarchical architecture (IPs, cores, subchips, chip). To test such SOCs and IoTs, DFT designers adopt new hierarchical test solutions across heterogeneous cores (memories, logic, AMS and interface IP), in order to support concurrent test, power reductions during test, DFT closure, isolated debug and diagnosis, pattern porting, calibration, and uniform access. This tutorial covers hierarchical test trends and solutions based on IEEE test standards, such as IEEE 1500, 1687 and 1149.1, along with intelligent infrastructure IP to help achieve the above advantages.

Tutorial 8:
TEST, DIAGNOSIS, AND ROOT-CAUSE IDENTIFICATION OF FAILURES FOR BOARDS AND SYSTEMS

by Krishnendu CHAKRABARTY, William EKLOW, Zoe CONROY

The gap between working silicon and a working board/system is becoming more significant and problematic as technology scales and complexity grows. The result of this increasing gap is failures at the board and system level that cannot be duplicated at the component level. These failures are most often referred to as "NTFs" (No Trouble Founds). The result of these NTFs can range from higher manufacturing costs and inventories to failure to get the product out of the door. The problem will only get worse as technology scales and will be compounded as new packaging techniques (SiP, SoC, 3D) extend and expand Moore's law. This is a problem that must be solved, yet, little effort has been applied up to this point. This tutorial will provide a detailed background on the nature of this problem and will provide DFT, test, and root-cause identification solutions at the board/system level. Practical insights from industry case studies will be highlighted and the presenters will show how recent research results from academia can help solve problems being faced by industry.

Tutorial 9:
STATISTICAL ADAPTIVE TEST METHODS TARGETING "ZERO DEFECT" IC QUALITY AND RELIABILITY

by Adit SINGH

Commercial applications continue to demand ever higher IC quality, most notably a "zero defect" target from automotive manufacturers. To cost effectively meet this challenge, innovative new statistical screening techniques improve test effectiveness by first identifying "suspect" parts, that are then more extensively tested, sometimes using tests that specifically target the suspected failure modes. Such adaptive tests exploit statistical correlations in process, performance and defect parameters. This tutorial presents a range of such test methodologies, and illustrates their effectiveness with results from recently published studies on production parts. Commercial tools from new companies in the "Adaptive Test" space are also discussed.

Afternoon

Tutorial 10:
MEMORY TEST & REPAIR IN NANOMETER ERA

by Manuel D'Abreu, Yervant ZORIAN

Recent growth in content creation has led to an explosion in the use of embedded memories. This tutorial will present a range of memories used, including RAMs and Non-Volatile memories (Flash) and how to ensure detection of today's defects upon manufacturing and during life time, including process variation and FinFET specific defects. BIST and Repair solutions to address yield optimization, endurance and data retention of failure modes will be presented. Given the tens of thousands of embedded memory instances in today's SOCs, the tutorial will also cover power management constraints, functional timing implications, test scheduling optimization, and area minimization options.

Tutorial 11:
COMBINING STRUCTURAL AND FUNCTIONAL TEST APPROACHES ACROSS SYSTEM LEVELS

by Artur JUTMAN, Hans-Joachim WUNDERLICH, Matteo SONZA REORDA

This tutorial introduces into the best practices, current challenges and advanced techniques of high quality system-level test and diagnosis. Specialized techniques and industrial standards of testing complex systems (which may correspond to a System on Chip, board or interconnected system) are introduced. The reuse for system test of design for test structures and test data developed at module level is discussed, including the limitations and research challenges. Structural test methods have to be complemented by functional test methods; hence, state-of-the-art and leading edge research for functional testing are covered. Solutions change depending on the scenario (manufacturing test or in field test) and the goal (test or diagnosis). The tutorial also discusses the role of standards and regulations in the area. Test cases are described and discussed.

Tutorial 12:
FROM DATA TO ACTIONS: APPLICATIONS OF DATA ANALYTICS IN SEMICONDUCTOR MANUFACTURING & TEST

by Haralampos STRATIGOPOULOS, Yiorgos MAKRIS

This tutorial seeks to elucidate the utility of data analytics in semiconductor manufacturing and test. Relevant concepts from data analytics theory will be introduced and agglomerated with current practice, showcasing their effectiveness on actual case studies with industrial data. A comprehensive survey of the relevant literature (including but not limited to the presenters' own work) will be provided, organized around four themes: (i) Test cost reduction through replacement of expensive tests by inexpensive alternatives and/or elimination of superfluous tests, either statically or adaptively during test application, (ii) Pre-deployment evaluation of candidate test methods through probabilistic test metrics, (iii) Post-production performance calibration through cost-effective knob tuning, and (iv) Yield learning and process monitoring through analysis of process variation impact on wafer-level spatial correlation.

Additional Information

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Paolo Bernardi

TTEP General Chair
Politecnico di Torino, I
Tel.: +39 011 564 7183
Fax: +39 011 564 7099
Email: paolo.bernardi@polito.it

Committee

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GENERAL CHAIR

P. BERNARDI – Politecnico di Torino

PROGRAM CHAIR

O. YAGLIOGLU – FormFactor Inc., USA

PAST CHAIR

D. GIZOPOULOS – University of Athens

FINANCE CHAIR

C.-H. CHIANG – Alcatel-Lucent

PUBLICITY CHAIRS

E. SANCHEZ – Politecnico di Torino

PLANNING CHAIR

Y. ZORIAN – Synopsis

INDUSTRIAL RELATIONS CHAIR

R. GALIVANCHE – INTEL Corporation

AUDIO/VISUAL CHAIRS

S. MENON – INTEL Corporation
O. SINANOGLU – NYU in Abu-Dhabi

ELECTRONIC MEDIA CHAIRS

S. DI CARLO – Politecnico di Torino
A. BOSIO – LIRMM

ORGANIZING LIASONS

Y. ZORIAN – ITC'15

PROGRAM COMMITTEE

Robert C. Aitken – ARM, USA
Davide Appello – STMicroelectronics, I
Kanad Chakraborty – Lattice Semiconductor, USA
Sreejit Chakravarty – LSI logic, USA
Kun Young Chung – Samsung, USA
Scott Davidson – Oracle, USA
Anne E. Gattiker – IBM, USA
Kazumi Hatayama – NAIST, J
Doug Josephson – Intel Corporation, USA
Hans Manhaeve – Qstar, B
Amit Majumdar – Xilinx, USA
Erik Jan Marinissen – IMEC, B
Stephen Sunter – Mentor, USA
Baosheng Wang – AMD, USA

For more information, visit us on the web at: http://ttep.tttc-events.org/ttep/tutorials.html

The Test Technology Educational Program 2015 is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC)